1. Field of the Invention
The present invention is directed in general to the field of semiconductor manufacturing. In one aspect, the present invention relates to the equipment for use in chemical mechanical polishing (CMP) in the manufacture of integrated circuits. Additional applications include, but are not limited to, substrate polishing, MR head polishing, or hard disk polishing.
2. Description of the Related Art
In the manufacture of integrated circuits on semiconductor wafers, various layers are formed over one another. Each functional layer is formed by additive and subtractive processes in which various materials are added (deposited) to the wafer surface and removed (etched or polished) from the wafer surface. Each layer can have material selectively removed (through the combination of photolithography and etch processes) to produce a desired pattern on a wafer resulting in a non-planar surface topography. Additional materials may be deposited on top of the non-planar surface that maintains a similar topography. At any given stage in the fabrication of an integrated circuit, the non-planar surfaces can adversely affect subsequent processing steps, can lead to device failure and can reduce yield rates. For example, when metal lines are formed over a semiconductor structure, any non-planar surfaces can impede the ability to remove metal from the structure where it does not belong.
A common process for smoothing surface irregularities and removing overburden material is through chemical mechanical planarization or chemical mechanical polishing (CMP). Overburden material refers to the excess deposited material on the high surface of a wafer that is necessary to completely fill the low or recessed surface regions on the wafer. The CMP process typically involves pressing a semiconductor wafer against a polishing pad at a controlled pressure, where either or both of the wafer and pad are rotating with respect to one another. By spinning the polishing pad while the semiconductor wafer is pressed against the polishing pad in the presence of a chemically active or abrasive material or liquid media (slurry), the upper surface of the semiconductor wafer is planarized and overburden removed to a desired target. With CMP equipment, the polishing pad typically includes a pressure sensitive adhesive layer which is used to affix the pad to a supporting platen structure. However, during the application of a polish pad on the platen, air pockets or bubbles can form between the adhesive and the platen, thereby causing raised areas or bulges in the polishing surface of the polishing pad. Such bulges in the pad create non-uniformities on the polished surface, and can cause the pad to breakthrough or slip/break wafers during the polishing process. In addition, the bulges cause uneven wear of the pad, which can decrease the run time for a pad, increase costs, increase tool downtime and increase manufacturing cycle time. Prior attempts to remove trapped air—such as by forcing the air bubbles out from under the pad with a roller or manually puncturing the bulges—have not been effective. Other solutions for eliminating air pockets under a polished pad have used grooves between the pad and platen to prevent air pockets from forming, but such solutions failed to prevent the intrusion of processing environment fluids between the platen and pad, which can adversely affect adhesion between the pad and platen, and can impair endpoint signal detection.
Accordingly, a need exists for an improved CMP equipment assembly that eliminates the entrapment of air between the platen and the polishing pad. In addition, there is a need to prevent infiltration of processing environment fluids from entering between the polishing pad and platen. There is also a need for an improved apparatus and device to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.